The present invention relates generally to integrated semiconductor memory cell capacitors. In particular, the invention relates to electrode compositions for memory cell capacitors incorporating high dielectric constant materials, and method of providing the same.
A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance, C=kk0A/d, where k is the dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode area and d is the spacing between the electrodes.
Integrated circuits in general, including DRAMs, are continually being scaled down in pursuit of faster processing speeds and lower power consumption. As the packing density of storage cells continues to increase, each capacitor must still maintain a certain minimum charge storage to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per footprint or unit of chip area occupied.
Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These techniques include increasing the effective surface area of the electrodes by creating folding structures such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive electrodes and capacitor dielectric conform. The surface of the electrodes may be further increased by providing a roughened surface to the bottom electrode over which the capacitor dielectric and the top electrode are conformally deposited.
Other techniques concentrate on the use of new dielectric materials having higher dielectric constants (k). Such materials include tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). These materials are characterized by effective dielectric constants significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k equals 3.9 for silicon dioxide, the dielectric constants of these new materials can range from 20 to 40 (tantalum oxide) to 300 (BST), and some even higher (600 to 800). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
Difficulties have been encountered, however, in incorporating these materials into fabrication process flows. For example, Ta2O5 is deposited by chemical vapor deposition (CVD) employing organometallic precursors in a highly oxidizing ambient. Additionally, after deposition the material must be annealed to remove carbon. This anneal is typically conducted in the presence of nitrous oxide (N2O), which is also highly oxidizing, while volatile carbon complexes are driven out.
Due to the volatility of the reactants and by-products of processes for forming high k materials, surrounding materials are subject to degradation. For example, polycrystalline silicon (polysilicon) capacitor plates are subject to oxidation, as are polysilicon or tungsten plugs below stacked capacitors, and the silicon substrate itself. While electrodes can be made of noble metals, such as platinum, oxygen tends to diffuse through such metal electrodes, such that surrounding oxidizable materials are still subject to degradation.
Oxidation of either the electrode or the underlying polysilicon plug reduces conductivity of these electrical elements, and has been viewed as a major obstacle to incorporating high k materials into integrated circuits. At the same time, memory cell capacitors must be electrically connected to integrated devices (e.g., transistors). Past efforts have therefore focused on using highly conductive diffusion barriers between the high dielectric material and the oxidizable elements such as polysilicon plugs. Solutions to date have not been satisfactory, however, and integrated capacitors incorporating high k materials have not demonstrated the desired reliability for incorporation into commercial memory devices.
Thus, a need exists for a capacitor structure and a process flow for reliably integrating high dielectric constant materials into memory cell capacitors.
In accordance with one aspect of the invention, a composition is provided for use in the fabrication of integrated circuits. The composition comprises a tantalum nitride material with a nitrogen content between about 7% and 40%.
In the illustrated embodiments, the tantalum nitride serves as an electrode for a capacitor, adjacent a high dielectric constant material such as Ta2O5, or as a barrier layer between such a capacitor and the underlying substrate. Advantageously, the composition provides conductivity while reducing oxidation of the electrode and surrounding conductive elements. In one embodiment, a tantalum nitride layer serves as the top or reference electrode of a capacitor, directly contacting a high dielectric material.
The tantalum nitride composition can take the form of a singular layer or a multiple layer structure. For example, a bilayer can be formed of a relatively thick, low nitrogen content sublayer which serves as a high conductivity current path, while a thinner, higher nitrogen content sublayer provides resistance to oxidation and to oxygen diffusion. Accordingly, the sublayer with higher nitrogen content directly contacts the high dielectric constant material in one embodiment.
Other aspects and advantages of the invention will be apparent from the Detailed Description below, and from the appended claims.